This invention is related to our co-pending application Ser. No. 07/585,811 filed September 20, 1990 for "Triple Polysilicon Flash Eprom Device".
This invention relates generally to semiconductor memory devices, and more particularly the invention relates to a triple polysilicon self-aligned split gate flash EEPROM cell.
A 5 volt only triple-poly flash EEPROM cell with a split gate structure is disclosed in Naruke, et al., "A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate On Its Source Side", Technical Digest of IEEE Electron Device Meeting 1988. As disclosed therein, a double polysilicon floating gate transistor is formed by first and second layers of polysilicon using conventional processing, and a select gate transistor is then formed by using an etching-back technology after depositing a third layer of polysilicon. The length of the select gate transistor is defined by the height of the double polysilicon floating gate transistor which is about 0.4 um. Due to the etching-back technology, the select gate transistor must run parallel to the control gate.
FIG. 1 illustrates the disclosed flash EEPROM cell. The flash EEPROM cell comprises N+ source region 11a and N+/N- drain region 11b separated by channel region 12. Channel region 12 consists of a portion 12a beneath the floating gate 13 and a portion 12b beneath the select gate 14. Overlying channel region 12 is gate dielectric 16a on which is formed the floating gate 13 and the select gate 14. Overlying floating gate 13 is insulation 16b, typically a composition layer of thermally grown oxide, deposited silicon nitride, and thermally grown oxide and nitride. A control gate 17 is formed on top of the insulation 16b. Typically both the floating gate 13 and the control gate 17 are formed of polysilicon. An insulation 16c is formed on the sidewall of the floating gate 13 and the control gate 17. The select gate 14 is formed by depositing the third layer of polysilicon and then by etching back the polysilicon to form a polysilicon spacer. The programming (high threshold voltage) of the cell is accomplished by raising the control gate to about 17 volts, the select gate to slightly above the threshold voltage of the select gate transistor which is about 1.5 volts, the drain to 5 volts, and the source to ground. The channel electrons are accelerated through a potential drop in between the select gate and the floating gate transistors. It is known that the hot electron injection efficiency using this method can be a thousand times higher than the conventional lateral acceleration method. Due to the high programming efficiency, the flash cell can be programmed with a lower drain voltage (5 volts) and with very low programming current (few micro-amperes). Erase of the cell is achieved by raising the drain region lib to 14 volts, grounding the control gate, and opening the source (floating). The high erase voltage can be obtained by using a charge pump technique from a 5 volt power supply. These features allow operation with a single 5 volt power supply.
Several major drawbacks in the prior art flash EEPROM of FIG. 1 relates to the formation of the select gate transistor. First, the split gate cell as disclosed in the prior art consists of two transistors which are the floating gate and the select gate. It takes the space of two transistors to form a single memory bit when it is implemented in a memory array. This is a common drawback for conventional split gate structure and imposes a major limitation for implementing a high density memory array. Second., the select gate is a polysilicon spacer which is formed by the polysilicon etching-back technique, and the length of the select gate is determined by the combined[height of the floating gate and the control gate which is about 0.4 um. Punchthrough of this transistor is very difficult to prevent with this small channel length, especially when the floating gate is over erased to a negative threshold. Third, the select gate is formed of polysilicon and it is very difficult to apply deposited polycide on a polysilicon spacer. Thus, in the prior art, only polysilicon with resistance around 20 to 30 ohm per square can be used for the select gate. As a result, the word line RC delay of a memory circuit is considerably longer than in the conventional memory circuit in which the polycide with resistance in the range of 2 to 4 ohm per square is used. Fourth, due to the etching-back method in the prior art, the select gate can only run parallel to the control gate. However, in a high density virtual ground array the select gate must be perpendicular to the control gate. Thus, the flash EEPROM cell in the prior art FIG. 1 cannot be implemented in a higher density virtual ground array structure.
As disclosed in our co-pending application Ser. No. 07/585,811 filed September 20, 1990 for "Triple Polysilicon Flash EPROM Device", a conventional virtual ground memory array as shown in FIG. 1B is formed by using the flash EPROM cell as disclosed in the above application. The channel length of the select gate transistor is non-self-aligned and is defined by using a photoresist as a bit line mask as shown in FIG. 1C. Due to the mis-alignment between the bit line mask and the stacked floating and control gates, the non-self-aligned select gate channel length is determined by the photoresist to floating gate edge dimensiona 19B and the mis-alignment tolerance (MA). Typically, the misalignment tolerance is in the range of 0.3 to 0.5 um which will be a major limitation for high density memory array. As shown in FIG. 1B, since each memory bit needs one bit line diffusion 18, one floating gate length 19A, and one non-self-align select gate length 19B+MA, the total dimension per memory bit is equal to 18+19A+19B + MA. It can be seen that in the conventional split gate virtual ground array as shown in FIG. 1B, each floating gate transistor needs one select gate transistor in which the select gate transistor is non-self-aligned to the floating gate edge. This indicates that the convention split gate virtual ground may have its limitation for implementing an ultra high density memory array.